CPU, GPU, primary memory and the fetch–decode–execute cycle – IB Computer Science exam questions with mark scheme

1Core4 marks

Describe the fetch stage of the fetch–decode–execute cycle, referring to the program counter (PC), memory address register (MAR), memory data register (MDR) and instruction register (IR). [4]

The address of the next instruction, held in the PC, is copied to the MAR(1)
The address is sent along the address bus to main memory/RAM (with a read signal on the control bus) and the instruction stored there is returned along the data bus to the MDR (buses need not be named for this mark; allow: the instruction at that address is fetched from memory into the MDR)(1)
The instruction is copied from the MDR to the IR (accept CIR)(1)
The PC is incremented to point to the next instruction (accept at any point in the description)(1)
Answer: PC → MAR; address bus to memory, instruction returned on data bus to MDR; MDR → IR; PC incremented.
Examiner tip: Name the register that holds each item and say what moves where (and on which bus); 'the CPU gets the instruction' earns nothing.

2Standard3 marks

A research team trains a neural network using a GPU. Explain why the architecture of a GPU makes it well suited to this task. [3]

A GPU has a very large number of (simpler) cores (allow: thousands of cores, compared with the few complex cores of a CPU)(1)
Training involves very many identical/independent calculations (e.g. matrix multiplications on weights) that can be carried out at the same time / in parallel (allow SIMD)(1)
So the calculations are completed much faster than on a processor executing largely sequentially (allow: high memory bandwidth / large dedicated memory keeps the many cores supplied with data)(1)
Answer: Many simple cores carry out the many identical matrix calculations in parallel, so training is much faster.
Examiner tip: Link the hardware feature (many cores) to the task (many parallel calculations); just saying 'GPUs are faster' is not enough.

3Standard3 marks

Explain how cache memory reduces the time the CPU spends waiting for data. [3]

Cache is small, very fast memory located on/close to the CPU (allow on the processor chip; L1/L2/L3)(1)
It stores copies of frequently/recently used instructions and data from main memory (allow: data likely to be needed next)(1)
If the CPU finds the data in cache (a cache hit) it avoids the slower access to RAM; only on a cache miss is RAM accessed(1)
Answer: Frequently used data held in fast memory near the CPU gives cache hits, avoiding slower RAM access.
Examiner tip: State 'cache hit' versus going to RAM; students lose marks by only saying cache is 'faster'.

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4Core3 marks

(a) State the function of the arithmetic logic unit (ALU). [1]

(b) Outline two functions of the control unit (CU). [2]

(a) Carries out arithmetic operations (e.g. addition, subtraction) and logical operations/comparisons (e.g. AND, OR, greater than) (need both arithmetic and logic/comparison; 'does calculations' alone is not enough)(1)
(b) Any one function from: decodes the instruction held in the IR / works out what it means; sends control signals (along the control bus) to coordinate/direct other components; synchronises the fetch–decode–execute cycle using the clock; controls the movement of data between registers, ALU and memory (ignore 'controls the computer' with no detail)(1)
(b) A second, different function from the same list(1)
Answer: (a) Performs arithmetic and logical/comparison operations. (b) e.g. decodes instructions; sends control signals to coordinate components/data flow.
Examiner tip: 'The CU controls the CPU' repeats the name and scores nothing; say what it controls and how (decoding, control signals, timing).

5Standard4 marks

A smart thermostat contains an embedded processor with both RAM and ROM. When it is switched on, it runs a start-up program and then records the current room temperature every minute.

(a) Explain why the start-up program is stored in ROM. [2]

(b) Explain why the temperature readings are stored in RAM rather than ROM. [2]

(a) ROM is non-volatile, so its contents are kept when the power is switched off(1)
(a) so the start-up instructions are available immediately every time the thermostat is switched on (allow: ROM is read-only so the start-up program cannot be accidentally changed/corrupted)(1)
(b) RAM can be written to / changed, but ROM is read-only (in normal operation)(1)
(b) the readings change every minute so must be written/overwritten repeatedly (allow: RAM is fast to read and write so the processor can access the readings quickly; ignore 'RAM is bigger')(1)
Answer: (a) ROM is non-volatile, so the boot program survives power-off and is ready at start-up. (b) Readings are constantly written/updated; RAM is read/write whereas ROM is read-only.
Examiner tip: Each answer needs a property of the memory AND why that property matters for this program or data, not just a list of properties.

6Standard5 marks

A program makes 2000 memory accesses while it runs. 1840 of these are cache hits. Reading from cache takes 2 ns. On a cache miss, the cache is checked first (2 ns) and then the data is read from RAM (80 ns).

(a) Calculate the cache hit rate as a percentage. [1]

(b) Calculate the total time, in ns, taken for all 2000 memory accesses. [2]

(a) 92(%) (1840 ÷ 2000 × 100)(1)
(b) Correct method: (1840 × 2) + (160 × 82) or 3680 + 13 120 (allow 1840 × 2 + 160 × 2 + 160 × 80)(1)
(b) 16 800 (ns) (allow 16.8 μs; 16 480 ns, from ignoring the 2 ns cache check on a miss, scores the method mark only)(1)
(c) The required data/instruction is not found in the cache, so it is fetched from (slower) main memory/RAM (allow from the next cache level, e.g. L2/L3)(1)
(c) A copy of it is placed/loaded into the cache (so that later accesses can be cache hits) / the CPU must wait longer (stall) for it(1)
Answer: (a) 92%. (b) 16 800 ns. (c) Data is fetched from RAM (or a lower cache level) and copied into the cache.
Examiner tip: The miss count is 2000 − 1840 = 160, and each miss costs 82 ns, not 80 ns, because the cache is checked first.

7Standard5 marks

The diagram shows how a CPU is connected to main memory by three buses, X, Y and Z. Arrowheads show the direction(s) in which each bus carries information.

(a) Identify bus X, giving a reason based on the diagram. [2]

(b) During the fetch stage, an instruction travels from RAM to the CPU along bus Y. Identify bus Y and the register that first receives the instruction. [2]

(a) Address bus(1)
(a) It is one-way/unidirectional: addresses are only sent from the CPU (MAR) to memory, never back(1)
(b) Data bus (it is two-way/bidirectional)(1)
(b) Memory data register/MDR (accept memory buffer register/MBR; do not accept IR or MAR)(1)
(c) Any one from: read signal; write signal; clock signal; interrupt (request); bus request/grant; reset (ignore 'control signals' with no example)(1)
Answer: (a) Address bus: one-way, CPU to memory only. (b) Data bus; MDR. (c) e.g. memory read / write signal.
Examiner tip: The data goes to the MDR first and only then is copied to the IR; naming the IR loses the mark.

8Hard6 marks

A simple CPU has the registers PC, MAR, MDR, IR and an accumulator (AC). Part of main memory is shown.

Address	Contents
20	LOAD 50
21	ADD 51
22	STORE 52
50	7
51	5
52	0

LOAD copies the value at the given address into AC; ADD adds the value at the given address to AC; STORE copies AC to the given address. Each instruction that refers to memory places that address in the MAR and passes the data through the MDR during the execute stage.

At the start, PC = 20 and AC = 0.

Copy and complete the table to show the contents of each register at the end of the execute stage of each instruction. [6]

Instruction	PC	MAR	MDR	IR	AC
LOAD 50
ADD 51
STORE 52

Row 1: PC = 21 and IR = LOAD 50(1)
Row 1: MAR = 50, MDR = 7 and AC = 7(1)
Row 2: PC = 22 and IR = ADD 51(1)
Row 2: MAR = 51, MDR = 5 and AC = 12(1)
Row 3: PC = 23 and IR = STORE 52(1)
Row 3: MAR = 52, MDR = 12 and AC = 12 (allow follow-through of an incorrect AC from row 2 for MDR and AC in this row)(1)
Answer: LOAD 50: 21, 50, 7, LOAD 50, 7. ADD 51: 22, 51, 5, ADD 51, 12. STORE 52: 23, 52, 12, STORE 52, 12.
Examiner tip: The PC is incremented during fetch, so at the end of each instruction it already holds the NEXT address; MAR and MDR end on the operand, not the instruction.

9HardHL only6 marks

A video-editing application exports a 4K video after applying colour-correction filters to every frame. The application uses both the CPU and the GPU.

(a) Explain how the CPU and the GPU divide the work and coordinate during the export. [4]

(b) Explain one difference between the way the CPU and the GPU access memory. [2]

(a) The CPU handles the sequential/control tasks, e.g. reading the project file, managing the timeline, encoding decisions, the user interface / operating-system calls(1)
(a) The GPU applies the filter to the pixels of each frame, a highly parallel task (the same operation on millions of pixels)(1)
(a) The CPU transfers/shares the frame data with the GPU (e.g. copies it over the PCIe bus into GPU memory/VRAM, or uses shared/unified memory)(1)
(a) The CPU issues commands/kernels to the GPU and waits for/synchronises with the results before writing the output file (accept the CPU schedules work so both run at the same time, e.g. CPU prepares the next frame while the GPU processes the current one)(1)
(b) A GPU has (dedicated) high-bandwidth memory designed to move large blocks of data to many cores at once / a CPU uses large multi-level caches to give low latency for individual accesses(1)
(b) so the GPU suits streaming whole frames of pixel data, while the CPU suits fast, unpredictable access to small amounts of data (latency vs throughput/bandwidth must be contrasted for this mark)(1)
Answer: (a) CPU runs the sequential control/encoding logic, transfers frames to the GPU and issues commands; GPU applies the filter to all pixels in parallel; CPU synchronises results. (b) GPU: high-bandwidth (VRAM) memory for throughput; CPU: large caches for low latency.
Examiner tip: Coordination marks need the data movement and the command/synchronisation step; 'the GPU does graphics' earns nothing.

10StretchHL only6 marks

The diagram shows three instructions, I1 to I3, passing through a four-stage instruction pipeline in a single CPU core. Each stage takes one clock cycle.

(a) State the stage that instruction I2 is in during clock cycle 3. [1]

(b) Calculate the number of clock cycles needed to complete 10 instructions (i) without pipelining and (ii) with this pipeline. [3]

(c) A quad-core processor has this pipeline in each core. 40 independent instructions are divided equally between the cores. Calculate the number of clock cycles needed, and state why the cores can work in this way. [2]

(a) Decode(1)
(b)(i) 40 (10 × 4)(1)
(b)(ii) Method: 4 cycles for the first instruction then 1 more for each of the remaining 9 / 4 + 10 − 1(1)
(b)(ii) 13(1)
(c) 13 (each core completes 10 instructions in 4 + 10 − 1 cycles; allow follow-through from (b)(ii))(1)
(c) Each core has its own pipeline/fetch–decode–execute hardware so the cores work independently and in parallel (because the instructions do not depend on each other)(1)
Answer: (a) Decode. (b) (i) 40 (ii) 13. (c) 13 cycles; cores have separate pipelines and run independent instructions in parallel.
Examiner tip: A pipeline does not divide the time by 4: the first instruction still needs all 4 stages before the others finish one per cycle.

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