Internal hardware, processor components, fetch–execute, interrupts and performance – A-level Computer Science exam questions with mark scheme

1Core4 marks

Describe the fetch stage of the fetch-execute cycle in a processor with a Von Neumann architecture. [4]

The address held in the program counter (PC) is copied to the memory address register (MAR) (allow: address sent along the address bus)(1)
The PC is incremented (to point at the next instruction) (allow at any point after the PC has been copied to the MAR)(1)
The instruction at that address is read from main memory (allow: read signal on the control bus) and copied via the data bus into the memory buffer register (MBR) (accept memory data register / MDR)(1)
The contents of the MBR are copied to the current instruction register (CIR) (accept MDR for MBR)(1)
Answer: PC to MAR; PC incremented; instruction from memory to MBR; MBR to CIR
Examiner tip: Name each register and say what moves into it; "the instruction is fetched" alone earns nothing.

2Core5 marks

(a) Name the bus that: [3]

(b) A processor has a 20-bit address bus. Calculate the number of memory locations it can address. [2]

(i) Address bus(1)
(ii) Data bus(1)
(iii) Control bus(1)
2²⁰ (one location per distinct address) (correct final answer with no working scores 2 marks)(1)
1 048 576 (accept 1 Mi / 1 mebi locations; reject 1 048 575, which is the highest address, 1 000 000, and 20 × 2 = 40)(1)
Answer: (a) address, data, control (b) 1 048 576
Examiner tip: Number of locations is 2 to the power of the bus width, not 20 × 2.

3Standard4 marks

A computer's performance is improved by adding more processor cores and a larger cache.

Explain how each change can improve performance. [4]

More cores allow more instructions to be executed at the same time (parallel processing)(1)
So different tasks or threads are processed simultaneously, so more instructions are completed per second / the total time taken is reduced (ignore a bare statement that software must be written to use multiple cores unless linked to this benefit)(1)
Cache is (small) memory that is faster to access than main memory, located on / close to the processor(1)
Larger cache holds more frequently used instructions/data, so fewer slower accesses to main memory (RAM) are needed (accept: higher hit rate)(1)
Answer: More cores: parallel execution; larger cache: more data quickly available, fewer main memory accesses
Examiner tip: Link each change to its mechanism; "faster" alone is not enough.

Book a free 30-minute session on WhatsApp and we'll find exactly which step is costing you the marks. Or build a timed paper on it.