Architecture of the CPU: components, registers, fetch-execute cycle – GCSE Computer Science exam questions with mark scheme

1Grade 1–34 marks

(a) State the purpose of the CPU. [1]

(b) Complete the table by writing the name of the register that matches each description. [3]

Description	Register
Holds the address of the next instruction to be fetched
Holds the address in memory currently being read from or written to
Holds the data or instruction that has just been fetched from, or is about to be written to, memory

(a) To process data / instructions; allow: to execute instructions / programs; allow: to carry out the fetch–(decode–)execute cycle. Do not accept 'the brain of the computer' on its own(1)
(b) Program Counter / PC(1)
(b) Memory Address Register / MAR(1)
(b) Memory Data Register / MDR; allow Memory Buffer Register / MBR(1)
Answer: (a) Processes data and instructions (fetch–decode–execute). (b) PC; MAR; MDR
Examiner tip: 'The brain of the computer' scores nothing – say what the CPU actually does: fetches, decodes and executes instructions.

2Grade 4–54 marks

Describe the steps that happen during the fetch stage of the fetch–decode–execute cycle. [4]

The Program Counter (PC) holds the address of the next instruction to be fetched(1)
This address is copied to the Memory Address Register (MAR); allow: the address is sent to memory (via the address bus)(1)
The instruction stored at that address is fetched / copied from memory (RAM) into the Memory Data Register (MDR); allow: the instruction is sent to the CPU (via the data bus) without naming MDR(1)
The Program Counter is incremented (by 1) to point to the next instruction; allow at any point in the answer(1)
Answer: PC holds address of next instruction → address copied to MAR → instruction at that address copied into MDR → PC incremented
Examiner tip: Name the registers and say what moves between them – vague answers like 'the CPU gets the instruction from memory' score at most one mark.

3Grade 4–54 marks

(a) Describe the role of the following CPU components. [2]

(i) Arithmetic Logic Unit (ALU)

(ii) Control Unit (CU)

(b) Explain how cache memory improves the performance of a CPU. [2]

(a)(i) ALU carries out arithmetic calculations (e.g. add, subtract) and logical operations / comparisons (e.g. AND, >); one needed(1)
(a)(ii) CU decodes instructions / sends control signals to coordinate the other components / controls (directs) the flow of data within the CPU / manages the fetch–execute cycle; one needed(1)
(b) Cache is (very) fast memory (on or close to the CPU) that stores frequently used / recently used data and instructions(1)
(b) …so the CPU does not have to fetch them from (slower) RAM, so instructions are fetched (and executed) faster / more instructions processed per second(1)
Answer: ALU does calculations and logic; CU decodes and controls; cache stores frequently used instructions so they are accessed faster than from RAM
Examiner tip: For cache, compare it with RAM – 'cache is fast' on its own is not enough; say it saves the CPU fetching from slower RAM.

4Grade 6–76 marks

A computer uses the von Neumann architecture.

(a) Explain what is meant by the von Neumann architecture. [2]

(b) The Program Counter (PC) holds the value 40. Memory address 40 contains the instruction LOAD 75, which copies the value stored at memory address 75 into the accumulator. Memory address 75 contains the value 12.

Complete the table to show the value held in each register at the end of the fetch stage for this instruction. [3]

Register	Value at end of fetch stage
Program Counter (PC)
Memory Address Register (MAR)
Memory Data Register (MDR)

(a) Any two from: uses the stored program concept / programs are stored in memory (main memory / RAM); data and instructions are stored in the same memory (in the same format / binary); instructions are fetched and executed one at a time (sequentially) by the CPU; the CPU contains registers such as the PC, MAR, MDR and accumulator(1)
(a) Second point from the list above(1)
(b) PC = 41(1)
(b) MAR = 40(1)
(b) MDR = LOAD 75 / the instruction LOAD 75; do not accept 12 or 75(1)
(c) 12; do not accept 75(1)
Answer: (a) Stored program concept: instructions and data held together in the same memory. (b) PC 41, MAR 40, MDR LOAD 75 (c) 12
Examiner tip: The MAR holds 40, the address of the instruction being fetched (the PC has already moved on to 41), and the accumulator receives the data 12 – not the address 75.

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